A Study of Fault-Tolerant Architecture Using Dynamic Partial Reconfiguration

Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa


Processors for embedded products are required to high reliability. Conventionally, it has been remained reliability by the redundant structure of circuits. However, it becomes larger overhead of the circuit area. In this article, we proposed reconfigurable fault tolerant architecture which can recovery from failure status with spare space. Especially, we aim to implement more simple fault tolerant architecture by using structure of dynamic partial reconfiguration. As a result, we discuss implementation of simple fault tolerant architecture.

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